The present invention relates in general terms a technique for transmitting or transferring data signals among a plurality of logic circuits. More particularly, the present invention is concerned with a technique for controlling or adjusting correctively a delay time (or time lag) involved in transmission of the data signal when variances thereof is noticeable, for thereby adjusting or regulating phase position of the data signal to a desired value upon reception thereof to realize a normal data transmission or transfer.
In the logic circuits or units such as those of a computer or the like, data signal transmissions or transfers (i.e., transmission/reception of the data signal) are performed among a plurality of logic circuits in synchronism with a clock signal. In that case, in order to ensure normal operations of these logic circuits, it is essentially required that the data signal as sent out from an addresser or sender logic circuit reach an addressee destination logic circuit, i.e., receiver logic circuit, within a prescribed time.
As the technique known heretofore in this conjunction, there may be mentioned a signal transfer method described, for example, WO96/29655. For having better understanding of the present invention, this prior art method will briefly be reviewed below.
FIG. 12 is a block diagram for illustrating the prior art method of transferring data signals among a plurality of logic circuits. In the figure, reference numeral 1201 denotes a logic circuit sending out a data signal (hereinafter also referred to simply as the sender logic circuit), and numeral 1202 denotes a logic circuit destined for receiving the data signal from the sender logic circuit 1201. Referring to the figure, a flip-flop circuit 1204 incorporated in the sender logic circuit 1201 is arranged to latch a data signal supplied from other circuit block 1203 in synchronism with a clock signal CK. The resultant output signal of the flip-flop circuit 1204 is sent out onto a wiring conductor 1206 through a driver circuit 1205. The receiver logic circuit 1202 receives the data signal through a receiver circuit 1207 incorporated in the receiver logic circuit 1202, which data signal is latched by a flip-flop circuit 1208 operating in synchronism with a clock signal CK2 to be conveyed to other circuit block equally incorporated in the receiver logic circuit 1202.
FIG. 13 is a timing chart for illustrating timing relations in the signal transmission described above. In this figure, reference symbols CK1 and CK2 designate the clock signals for the sender and receiver logic circuits mentioned above, D1 designates an output signal of the flip-flop circuit 1204 of the sender logic circuit 1201, D2 designates an input signal to the flip-flop circuit 1208 of the receiver logic circuit 1202, and D3 designates an output signal of the flip-flop circuit 1208.
Referring to FIG. 13, assuming that the system now under consideration is to be so designed that the signal D3 be outputted from the flip-flop circuit 1208 after the time lapse of two cycles in terms of the clock period as of the time point at which the signal D1 is outputted from the flip-flop circuit 1204, it is then required that the flip-flop circuit 1204, the driver circuit 1205, the wiring conductor 1206 and the receiver circuit 1207 have to be so designed as to involve the respective delay times so that the condition given by the undermentioned expression can be satisfied.
Tck less than Td less than 2xc3x97Tckxe2x80x83xe2x80x83Exp. 1 
where Tck represents the clock period and Td represents a delay time or time lag intervening between the aforementioned signals D1 and D2 (inclusive of the delay time incurred by the flip-flop circuit 1204).
In the conventional logic circuit system described above, it is however noted that the signal delays brought about by the circuits such as the flip-flop circuit 1204, the driver circuit 1205, the receiver circuit 1207 and others as well as the delay incurred by the wiring conductor 1206 may vary due to variance of the respective manufacturing processes. In that case, the condition given by the above-mentioned expression Exp. 1 can no more be satisfied, giving rise to a problem that the data signal transmission as designed can not be realized, to a great disadvantage.
FIG. 14 is a timing chart for illustrating, by way of example, influence which makes appearance when the delay time Td varies or increases by xcex94Td in the logic circuit system shown in FIG. 12. In this case, the undermentioned expression Exp. 2 will apply valid, as can be seen in FIG. 14.
(Td+xcex94Td) greater than 2xc3x97Tckxe2x80x83xe2x80x83Exp. 2 
Apparently, the condition given by the expression Exp. 1 is not satisfied. That is to say, the signal D3 is not outputted from the flip-flop circuit 1208 after lapse of two cycles in terms of the clock period but outputted after three cycles of the clock period, which obviously differs from the requirement imposed in design.
In the light of the state of the art described above, it is an object of the present invention to solve the problem mentioned above by providing a logic circuit equipped with a phase-controlled data receiving interface for realizing the data transfer or transmission within a desired or designed time period through an automatic delay regulating control even in the case where the delay time involved in the data signal transmission should vary due to variances brought about in the manufacturing processes or for other causes.
Another object of the present invention is to provide an improved structure of logic circuit which makes it possible to carry out data reception under prescribed timing by absorbing variations of the delay time involved in the data signal transmission which exceeds the clock period.
In view of the above and other objects which will become apparent as the description proceeds, there is provided according to an aspect of the present invention a logic circuit which is comprised of a signal phase controller including a signal phase detection circuit for deciding or detecting the arrival of a signal to be received from external at a detecting time point predetermined as based on a clock signal which provides a basis for the signal receiving operation and a variable delay circuit whose delay factor or quantity is controlled in dependence on the result of the detection performed by the above-mentioned signal phase detection circuit, and a flip-flop circuit designed for latching the signal passed through the above-mentioned variable delay circuit in synchronism with the clock signal.
In a mode for carrying out the present invention, the signal phase detection circuit mentioned above may be so designed as to detect or decide the arrival of the signal to be received by detecting discriminatively whether the signal received is at level xe2x80x9cHxe2x80x9d (high level) or xe2x80x9cLxe2x80x9d (low level). However, with this arrangement, detection or decision as to arrival of the signal for reception can not be effectuated when the logical level xe2x80x9c0xe2x80x9d or alternatively xe2x80x9c1xe2x80x9d of the received signal continues successively. Thus, according to another mode for carrying out the present invention for coping with the situation mentioned above, a test signal is transmitted during a regulation period in place of the signal to be transferred intrinsically and a phase control is carried out completely in the receiver logic circuit during the regulation period in which the test signal is being transferred.
Thus, in a first embodiment of the present invention, the test signal mentioned above assumes a high level (level xe2x80x9cHxe2x80x9d) during one period of the clock signal while assuming low level (level xe2x80x9cLxe2x80x9d) during a succeeding period of the clock signal, wherein alteration of the levels xe2x80x9cHxe2x80x9d and xe2x80x9cLxe2x80x9d is repeated. By virtue of this arrangement, there can be realized the phase control which is capable of compensating for variation or change of the delay time so far as it falls within one period of the clock signal.
In another preferred embodiment of the present invention, a test signal which assumes the level xe2x80x9cHxe2x80x9d (high level) during a period corresponding to two periods of the clock signal while assuming succeedingly the level xe2x80x9cLxe2x80x9d (low level) during a succeeding period corresponding equally to two periods of the clock signal in a repetitive sequence is sent to the receiver logic circuit from the sender logic circuit with a view to compensating for variation of more noticeable time delays involved in the signal transmission.
In yet another preferred embodiment of the present invention, the signal phase controller provided in association with the receiver logic circuit is constituted by a plurality of phase control units interconnected to one another. A detection timing signal is applied simultaneously to these phase control units, each of which then responds thereto by performing simultaneously a phase control operation. To this end, each of the phase control units may include an adjustable or variable delay circuit and a signal phase detection circuit, wherein the signal phase detection circuit is so designed as to detect or decide the arrival of the test signal at a location on the output side of the variable delay circuit at a time point or timing commanded by the detection timing signal, to thereby output a delay control signal. On the other hand, each of the variable delay circuits is designed to impart selectively either one of two delay amounts or quantities to the signal passing therethrough, wherein selection of the delay quantity mentioned above is commanded-by the delay control signal supplied from the signal detection circuit.
In a further preferred embodiment of the invention, the phase control circuit may equally be constituted by a plurality of phase control units interconnected to one another. Sequentially applied to the individual phase control units from the upstream side to the downstream side is a detection timing signal for forcing the phase control units to perform phase control operation in a sequential manner. Each of the phase control units includes a variable delay circuit and a signal phase detection circuit, wherein the signal phase detection circuit is designed to detect the passage of the test signal at a location on the output side of the variable delay circuit to thereby generate the delay control signal, as in the case of the mode described just above. The variable delay circuits connected in cascade have respective delay quantities which differ from one to another. More specifically, the delay quantities of the individual variable delay circuits are so set as to increment proportionally at an equal rate as viewed toward the upstream side. To say in another way, the phase control operations are carried out sequentially as a whole, wherein it is determined whether the delay quantity is to be imparted or not for the phase control while changing sequentially the delay quantity from rough to a fine value.
The above and other objects, features and attendant advantages of the present invention will more easily be understood by reading the following description of the preferred embodiments thereof taken, only by way of example, in conjunction with the accompanying drawings.